The present invention generally relates to a storage device.
In recent years storage elements have been disclosed in which, by applying a voltage across for example two opposing electrodes to cause ionization of the metal material at the surface or in the interior of one of the electrodes, and causing the ions thus created to be diffused in the direction of the opposing electrode, the resistance value across the two electrodes becomes a resistance value different from the resistance value prior to the application of voltage, so that information with two or more values can be recorded by means of such changes in resistance values (see Publication of the Japanese translation of the PCT application 2002-536840).
The specific structure of such a storage element is shown in FIG. 1. FIG. 1 is an enlarged cross-sectional view of a storage element.
The storage element 35 has a structure in which an intra-electrode material layer 33 is enclosed between, for example, two electrodes (a first electrode 31 and a second electrode 32).
In a storage element 35 with such a structure, by for example using an ionic conductor as the intra-electrode material layer 33, and in addition by making one of the two electrodes 31, 32 (for example, the first electrode 31) include a metal which diffuses as an ion during ionic conduction, when a voltage is applied across the two electrodes 31, 32 of the storage element 35 electric charge is supplied to the intra-electrode material layer 33, and as a result of diffusion as ions of the metal included in the electrode 31 into the intra-electrode material layer 33 composed of the ionic conductor, the resistance, capacitance and other electrical characteristics of the ionic conductor change, and information storage operation is possible.
In FIG. 1, a storage element 35 is shown with a structure in which the intra-electrode material layer (ionic conductor) 33 alone is enclosed between the first electrode 31 and second electrode 32; however, a storage element may also have a structure, not shown, in which for example an intra-electrode material layer (ionic conductor) and a barrier layer are enclosed between a first electrode and second electrode.
Next, operation of recording information in such a storage element is explained in detail.
A recording operation in which the resistance value of the storage element is changed from a high state to a low state is defined as information “writing”, and an operation in which the resistance value of the storage element is changed from a low state to a high state is defined as information “erasure”.
The resistance value of a storage element in a state in which information has not been written shall be assumed to be in the high-resistance state.
First, when writing information, for example a voltage equal to or above a certain threshold value is applied to for example the first electrode 31 of the storage element 35.
When a voltage equal to or above a threshold value is applied to the first electrode 31 in this way, the metal included in the first electrode 31 and which is electrochemically active diffuses as cations into the intra-electrode material layer 33. Then, the cations diffused into the intra-electrode material layer accept electrons from the second electrode 32 and are precipitated, to form an electrical precipitate (electronic conduction path). Accordingly, the resistance value of the intra-electrode material layer 33 between the first electrode 31 and the second electrode 32 enters a low-resistance state. That is, the state in which information has been written to the storage element 30 is entered.
On the other hand, when erasing previously written information a voltage is applied to the second electrode 32 such that the electrical precipitate which had been formed in the intra-electrode material layer 33 as described above is dissolved.
When such a voltage is applied to the second electrode 32, the electrical precipitate formed in the intra-electrode material layer 33 is dissolved and disappeared, and the resistance value of the intra-electrode material layer 33 between the first electrode 31 and the second electrode 32 returns to its original high resistance value. That is, the information previously written to the storage element 35 is erased.
By means of such changes in resistance value, operations of writing information in the storage element 35 are performed.
However, when the above-described storage element is for example used to constitute a storage device, problems such as those described below are anticipated to occur.
First the configuration of a conventional storage device (for example DRAM) is explained in conjunction with FIG. 2, and then the reasons for the anticipated occurrence of problems are explained in detail.
In a conventional storage device (for example DRAM) 41, as shown in FIG. 2, a plurality of storage cells 42 are arranged in the column direction (vertical direction) and in the row direction (horizontal direction), to form a storage cell array 43. A storage element 45 is provided in each storage cell 42.
In such a storage device 41, in order to select an arbitrary storage cell 42 from the storage cell array 43 and perform recording to or reading from the storage element 45 of that storage cell 42, for example bit lines B to select an arbitrary column of the storage cell array 43, and word lines W to select an arbitrary row, are provided.
In addition, active elements (access transistors) 46 composed for example of a MOS transistor to control accessing of storage elements 45, and power supply lines 44 to supply a power supply voltage and ground voltage to storage elements 45, are provided.
The bit lines B are for example also so-called data lines when recording information in or reading recorded information from storage elements 45; the word lines W are for example also so-called control lines to put access transistors into the ON state or to the OFF state.
In a storage device 41 with such a configuration, information is recorded in a storage element 45 only when for example a control voltage is applied to the word line W connected to the gate G of the access transistor, and the access transistor 46 is put into the ON state.
When for example information is to be recorded to a storage element 45, by executing control through the access transistor 46, voltage, current and similar are supplied to the storage element 45.
When a plurality of storage elements 35 having a structure as shown in FIG. 1 are used to constitute such a storage device 41, and an operation of recording information in an arbitrary storage element 35 is performed similarly to the operation described above, the access transistor 46 provided together with the storage element 35 in a storage cell 42 becomes large.
That is, in the storage element 35 shown in FIG. 1 the resistance value after the performance of information writing becomes a low resistance value of approximately 200 Ω, and the threshold value for the voltage applied to a storage element 35 when erasing previously written information is several hundred millivolts (for example, approximately 200 mV to 300 mV) (see the above Publication of the Japanese translation of the PCT application 2002-536840).
Hence in the storage device 41, when performing erasure in the storage element 35 of an arbitrary storage cell 42 under such conditions, a voltage equal to or greater than the threshold value of the storage element 35 (200 mV) is applied, so that it is necessary to pass a current of 1.0 mA or greater through the access transistor for supply to the storage element 35.
According to the “roadmap” of the ITRS (International Technology Roadmap for Semiconductors), which indicates various characteristics of conventional transistors arranged by year, in the interval from 2001 to 2006, for example, reductions in the design rule of semiconductor devices will advance from the 130 nm generation to the 70 nm generation; however the power supply voltages used will be constant at approximately 1.0 V, while current capacities are expected to be constant at approximately 600 μA per micrometer of channel width.
Hence when for example a power supply voltage of 1.2 V and transistors with design rule in the 130 nm generation (MOS transistors) are used in the storage device 41, in order to supply a current equal to or exceeding 1 mA to a storage element 35 through an access transistor 46 when erasing previously written information, according to the ITRS roadmap it is necessary to provide a transistor with a channel width of approximately 1.7 μm in each storage cell 42.
In such a case the area of a storage cell 42 becomes far larger than for example that of a DRAM storage cell designed with the same design rule.
However, inventors of the present invention used a writing method using voltage pulses which is capable of writing information in shorter amounts of time than the writing method by voltage sweeping disclosed in the above publication, to write information to both the storage element 35 disclosed in the above publication the cross-section of the intra-electrode material layer 33 of which has a diameter of 4 μm and to a storage element the cross-section of the intra-electrode material layer of which has a diameter of 0.5 μm as a comparative example, and the state of the resistance value of the storage element after the information writing was performed was investigated.
As a result of investigating in this way the state of the resistance value of a storage element after information writing using a voltage pulse writing method, and more specifically under the conditions of for example an applied voltage of 1.0 V and writing time of 100 msec, the resistance value of the storage element after writing was performed was 2.0 kΩ in both the storage elements. That is, those inventors discovered that the resistance value of a storage element after information writing is performed does not depend on the cross-sectional diameter of the intra-electrode material layer.
Accordingly with the storage element structure disclosed in the above publication, for example, and under the writing conditions disclosed, even if writing is performed to a storage element of smaller design than the case in which the cross-sectional diameter of the disclosed intra-electrode material layer is 4 μm, because as described above the resistance value of the storage element after writing does not depend on the cross-sectional size of the intra-electrode material layer, the resistance value of the storage element after writing remains the same value as the resistance value (200 Ω) of a storage element of diameter 4 μm, as disclosed in the above publication.
Further, in the above publication an electron conduction path is disclosed which, as an electron conduction path formed for example by the performance of information writing, has a considerably small area of cross-section.
This fact corroborates the fact discovered by the inventors that the resistance value of a storage element after information writing does not depend on the cross-sectional area of the intra-electrode material layer, and also the fact that, for the storage element structure disclosed in the above publication, under the disclosed writing conditions, even when the cross-sectional size of the disclosed intra-electrode material layer is of diameter 4 μm, and even when information is written to a more finely designed storage element, it is reasonable that the resistance value remain at 200 Ω.
Thus even when for example the storage device 41 is decreased in size, the resistance value of the storage elements 35 to which information has been written remains at the low resistance value of 200 Ω; hence as described above, in order to supply a current of 1 mA or greater to a storage element 35 through an access transistor 46, the need arises to provide a large access transistor in each storage cell 42.
In such a case also, as described above, the area of the storage cell 42 becomes much larger than that of for example a DRAM storage cell designed with the same design rule.
Thus in the storage device 41 it is necessary to supply a large current when the resistance value of a storage element 35 after information has been written is low, and the written information cannot easily be erased.
On the other hand, in order to facilitate erasure of previously written information, the resistance value of a storage element 35 to which information has been written can be increased.
However, when the resistance value of a storage element 35 to which writing has been performed is high, an operation of for example reading the written information is delayed.
This is true for all storage devices when operations of recording information are performed by changing the resistance value of a storage element 35.
Below, the reason for such a lengthening of the time required for reading information is explained, together with the configuration of the read circuit shown in FIG. 3 and actual reading operation.
As explained below, the read circuit shown in FIG. 3 is a certain case with the minimum circuit configuration necessary when information written to a storage element 35 in for example the storage device 41 shown in FIG. 2 is read as either a data “00” or a data “01”.
The read circuit 60 includes, for example, transistors for control (switching transistors) 61, 611 provided near the entrance, load circuits 62, 621 which convert the current flowing in a bit line B (cell current) into a voltage, and a sense amplifier 63 to detect information written to the storage elements 35, 351 of each storage cell 42, 421, connected by wiring, where the information is written to the storage elements 35, 351 by executing control through access transistors 46, 461.
The storage cell 421 provided on the right side in the drawing is a so-called reference cell used to compare the states of cell currents flowing in the bit lines B when reading information which has been written to the storage element 35 of the storage cell 42 provided on the left side in the drawing.
Other portions are similar to those in the storage device 41 shown in FIG. 2, and so the same symbols are assigned to corresponding portions.
Here the storage element 35 is assumed to be configured such that when for example writing information, by controlling the writing conditions, the low-resistance state can be created in an intermediate stage of the resistance change.
That is, it is assumed that when the resistance value of a storage element 35 to which information has not been written is for example 100 kΩ, by controlling the write conditions, a low-resistance state of for example 50 kΩ, 20 kΩ, or 10 kΩ can be created.
In the state in which the 100 kΩ storage element 35 holds the data “00”, the resistance value at this time is taken to be Rmhigh; in the state in which the 50 kΩ storage element 35 holds the data “01”, the resistance value at this time is taken to be Rmlow1; in the state in which the 20 kΩ storage element 35 holds the data “10”, the resistance value at this time is taken to be Rmlow2; and in the state in which the 10 kΩ storage element 35 holds the data “11”, the resistance value at this time is taken to be Rmlow3.
Thus in such a storage element 35 with a structure enabling the creation of low-resistance states at intermediate stages of resistance change, a single storage element 35 can hold two bits of data.
Here a read operation is considered for the state in which the data “00” is held, that is, when the storage element 35 is in the high-resistance state Rmhigh.
In the read circuit 60 for example, the current flowing in the bit line B from the power supply line 44 passing through the storage element 35 (the cell current) is detected to be “extremely small” or “zero” by the sense amplifier 63.
Hence by performing a read operation, if the current flowing in the bit line B is regarded as “extremely small” or “zero”, then the storage element 35 is judged to be in the high-resistance state, as described above.
Thus reading of the state in which data “00” is held is comparatively simple, and there is little possibility of erroneous reading of for example data other than the data “00”.
However, when a storage element 35 is in a state of holding data “01” (that is, when the resistance value of the storage element 35 is changed from high resistance to a low resistance), in order to read the data held, the magnitude of the current (cell current) flowing in the bit line B from the power supply line 44 through the storage element 35 is judged to be greater than or smaller than the current in the above-described state of holding data “00”.
Alternatively, for purposes of contrast, a judgment can be made as to whether the above cell current is equal to, for example, the current (cell current) flowing in the bit line B from the power supply line 44 through the storage element 351 of a reference cell 421 to which data “01” has been written.
In order to make the judgment accurately, it is necessary to wait for a certain length of time before detecting the change in current in bit line B, or before detecting the change in voltage when for example current/voltage conversion is performed in the load circuit 621.
In the storage element 35, when, although the resistance is lower than the state in which for example the data “00” is held, the absolute magnitude of the low resistance is high, it is difficult to perform the detection rapidly.
This is attributed to the fact that when the resistance value is high the current flowing in the bit line B through the storage element 35 is small, so that the parasitic capacitance associated with the bit line B is not charged rapidly, and as a result there is a large delay in the change in potential of the bit line B.
In other words, the cause is that the time constant is large, so that there is a large delay in the change in potential of the bit line B.
In addition, when a storage device is considered in which information with more than two values can be recorded, with, for example, a state in which the resistance is still lower than the state in which data “01” is held as a state of holding data “10” (binary), and a state in which the resistance is still lower than this as a state of holding data “11” (binary), while there is little possibility of erroneous reading as a state of holding other than data “00” when the resistance is at the highest value, that is, when data “00” is held, in the state with second-highest resistance, that is when data “01” is held, due to the delay in potential change in the bit line there is the greatest difficulty in rapidly judging the data value.
Thus in the storage device 41, when the resistance value of a storage element 35 after writing of information is high, the time required when reading the information written to the storage element 35 becomes long.